1. Field of the Invention
This invention relates to a dynamic semiconductor memory and in particular to a dynamic semiconductor memory having a refresh control circuit therein.
2. Related Art Statement
Capacity of a semiconductor memory has been increased at the rate of quadruple every three years. 64 megabit dynamic RAM (DRAM) has already been reported in an academic society of this field. With the increase of their capacity, semiconductor memories have been widely used in many devices such as portable personal computer and word processor. Conventionally, a static RAM (SRAM) has first been used for such applications because of small consumption of electrical power. However, these days DRAM is used instead of SRAM for the purpose of reducing costs because DRAM is cheaper than SRAM for equal amount of capacity. However, DRAM consumes larger electrical power than SRAM because DRAM needs periodic refresh in order to maintain data to be stored in a memory cell. For compensating for this defect, a refresh period is made longer in stand-by condition to decrease consumption of electrical power. For instance, though standard refresh period is 16 milliseconds in 4 megabit DRAM, some of them adopt refresh period of 128 milliseconds, eight times as longer as the standard period, to decrease consumption of electrical power with the result that its consumption of electrical power is decreased to be less than one fifth of standard version. Thus, if the refresh period is made longer, consumption of electrical power can be decreased. However, this brings a problem of excessive requirement for data retention characteristics and so on.
DRAM is developed every generation to have storing capacity four times as large as the previous generation and the number of refresh cycle twice as great as the previous generation. Accordingly, the refresh cycle is doubled to maintain the refresh time to be in a constant rate for all operation time. Therefore, a memory cell is inevitably required to have data retention characteristics twice as long as the previous generation, and additionally required to have the characteristics more than twice as long as the previous generation for reducing consumption of electrical power. On the other hand, a memory cell is small-sized for high density packaging, and thus storing capacity of such a memory cell is decreased relative to the previous generation. In addition, capacitive dielectric film becomes thinner to compensate for reduced storing capacity. These situations make it difficult to reduce leak of current happened inside a memory cell. Thus, though it is easy to just prolong the refresh period, a memory cell is required to have enhanced data retention characteristics, and it is not easy to fabricate the memory cell having such characteristics.
Most of electrical power consumed by DRAM includes charging and discharging current of several parasitic capacitance, transit through current flowing between transistors and little of steady-state current. Thus, longer operation cycle time reduces consumption of current in inverse proportion. Accordingly, if the refresh period is made longer, it is possible to prolong operation cycle time because the number of refresh cycle during that time is constant, thereby consumption of power being able to be reduced.
For instance, in the case of 4 megabit DRAM, data retention characteristics are not uniform, but widely vary. Data retention characteristics measured at room temperature is represented in FIG. 1 wherein the axis of abscissa represents data retention time and the axis of ordinate represents the number of cumulation of inferior bits, both axes being expressed in logarithm. The most inferior bit has only about 1 second of retention time, while the number of cumulation of inferior bits at 100 seconds of retention time is just hundreds of bits, which is just not more than one hundred thousandth relative to 4 megabit.
Data retention time for 4 megabit DRAM is standardized to be 16 milliseconds. Since this value is a minimum at 70 degrees centigrade at which retention characteristics are deteriorated because of high temperature, this standard cannot be met with unless the retention characteristics are at least 0.5 seconds at a room temperature. That is, though 99.9% or more of bits have characteristics not less than hundred times as sufficient as the standard, refresh of all bits has to be done in shorter periods because of a few inferior bits.
FIG. 2 shows a structure of such a conventional dynamic semiconductor memory.
The dynamic semiconductor memory has a buffer circuit 1 for receiving RAS (row address strobes) and CAS (column address strobes) and buffer amplifying them; a CBR identifying circuit 2 for producing refresh mode signals RM at active level when it detects that a mode is CBR (CAS Before RAS) refresh mode on the basis of output signals transferred from the buffer circuit 1; a refresh address signal generating circuit 4 for producing refresh address signals RAD when the refresh mode signal RM is at active level; an internal control signal producing circuit 3b for receiving the output signals emitted from the buffer circuit 1, the refresh mode signal RM and timing signal TS emitted from the refresh address signal generating circuit 4 to generate activation control signal .phi. which is introduced to be at activated level at a predetermined timing; an address buffer circuit 5 for receiving an external address signal AD to output external address signals ADr and ADc; a switch circuit 6 for selecting the refresh address signal RAD if the refresh mode signal RM is of active level while selecting the external address signal ADr if the refresh mode signal RM is of inactive level; memory cell arrays 9a and 9b each having a plurality of memory cells, word lines and bit lines; row selecting circuit having row decoders 7a and 7b and word driving circuits 8a and 8b for being activated when the activation control signal .phi. is of activated level, to put a predetermined word line in the associated memory cell array 9a, 9b to be on selection level; sense amplifying circuits 11a and 11b for being activated when the activation control signal .phi. is of activated level, to amplify and rewrite data stored in a memory cell through the bit lines, the cell connecting with a word line of selection level of associated memory cell arrays 9a and 9b; a column decoder 10 for selecting a predetermined bit line in the memory cell array 9a, 9b in accordance with the external address signal ADc emitted from the address buffer circuit 5; and an input and output circuit 12 for transferring data DI, which is externally input and to be written therein, to a determined bit line and outputting readout data transferred through the determined bit line.
In the case of 4 megabit DRAM, the external address signal AD is 11 bits and this is divided by time-sharing into row address signals ADr and column address signals ADc. Accordingly, a matrix having 2048 rows and 2048 columns is created. However, refresh is determined to be done every 1024 cycle by 10 bits of the row address signals ADr. Therefore, as illustrated in FIG. 2, a pair of the row decoders 7a and 7b and a pair of word driving circuit 8a and 8b both for driving 1024 word lines are provided. They simultaneously drive word lines in each of the memory cell arrays 9a and 9b.
As aforementioned, in a conventional dynamic semiconductor memory, the pair of memory cell arrays 9a and 9b are adapted to be refreshed at the same period and the same timing. Thus, even if there is no memory cell having inferior data retention characteristics in one of memory cell arrays, they both have to be refreshed at the same period, thereby causing it difficult to reduce consumption of electrical power during refreshing.